stos/amd64: lapic: Add support for IPIs

Signed-off-by: Chloe M. <chloe@mensia.org>

paw/stos/arch/amd64/cpu/lapic.c

@@ -11,6 +11,7 @@
 #include <machine/msr.h>
 #include <machine/cpuid.h>
 #include <hal/mmio.h>
+#include <hal/prim.h>
 #include <drivers/acpi/tables.h>
 #include <drivers/acpi/acpi.h>
 #include <mm/vmm.h>
@@ -135,9 +136,66 @@ LapicEnable(MCB *Mcb)
     DTRACE_BSP("enabled %s %s\n", type, mode);
 }
 
+VOID
+MdLapicSendIpi(UCHAR Vector, UCHAR DestId, BOOLEAN LogicalDest,
+    IPI_SHORTHAND Xnd, IPI_DELMOD DelMod)
+{
+    KPCR *ThisCore;
+    MCB *Mcb;
+    ULONG IcrLow, IcrHigh;
+    ULONG Icr = 0;
+
+    /*
+     * If the shorthand is refering to ourselves and we are x2APIC we
+     * can use a better path via its specialized SELF IPI MSR.
+     */
+    ThisCore = HalKpcrCurrent();
+    if (Xnd == IPI_XND_SELF && Mcb->HasX2Apic) {
+        MdWrmsr(LAPIC_SELF_IPI, Vector);
+        return;
+    }
+
+    Mcb = &ThisCore->Mcb;
+
+    /* Clamp these fields */
+    DelMod &= 7;
+    Xnd &= 3;
+
+    /* Encode the ICR */
+    Icr |= Vector & 0xFF;
+    Icr |= Xnd << 18;
+    Icr |= DelMod << 8;
+    Icr |= LogicalDest << 11;
+
+    /* For xAPIC only */
+    if (!Mcb->HasX2Apic) {
+        IcrHigh = ((UQUAD)Icr >> 32) & (ULONG)-1;
+        IcrLow = Icr & (ULONG)-1;
+        IcrHigh |= (UQUAD)DestId << 24;
+
+        LapicRegWrite(Mcb, LAPIC_ICRHI, IcrHigh);
+        LapicRegWrite(Mcb, LAPIC_ICRLO, IcrLow);
+
+        /* Only on legacy xAPICs do we poll */
+        for (;;) {
+            Icr = LapicRegRead(Mcb, LAPIC_ICRLO);
+            if (ISSET(Icr, IPI_DELSTAT_PENDING))
+                HalCpuSpinWait();
+        }
+
+        return;
+    }
+
+    /* On x2APICs only as it queues */
+    Icr |= (UQUAD)DestId << 32;
+    LapicRegWrite(Mcb, LAPIC_ICRLO, Icr);
+}
+
 VOID
 MdLapicInit(KPCR *Kpcr)
 {
+    INTR_HANDLER Handler;
+    INTR_DATA *IntrData;
     ACPI_MADT *Madt;
     MCB *Mcb;