stos/amd64: lapic: Detect if x2APIC mode is present
Signed-off-by: Chloe M. <chloe@mensia.org>
This commit is contained in:
@@ -43,6 +43,19 @@ LapicIsSupported(VOID)
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return ISSET(Edx, BIT(9)) != 0;
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return ISSET(Edx, BIT(9)) != 0;
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}
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}
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/*
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* Returns true if the CPU can operate its Local APIC unit
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* in the newer x2APIC mode.
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*/
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static BOOLEAN
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LapicHasX2Apic(VOID)
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{
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ULONG Ecx, Unused;
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CPUID(1, Unused, Unused, Ecx, Unused);
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return ISSET(Ecx, BIT(21)) != 0;
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}
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/*
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/*
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* Enable the Local APIC unit
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* Enable the Local APIC unit
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*/
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*/
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@@ -85,6 +98,7 @@ MdLapicInit(KPCR *Kpcr)
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Mcb = &Kpcr->Mcb;
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Mcb = &Kpcr->Mcb;
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Mcb->LapicBase = PMA_TO_VMA((UPTR)Madt->LapicAddr);
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Mcb->LapicBase = PMA_TO_VMA((UPTR)Madt->LapicAddr);
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Mcb->HasX2Apic = LapicHasX2Apic();
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/* Enable the Local APIC */
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/* Enable the Local APIC */
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LapicEnable();
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LapicEnable();
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@@ -18,11 +18,13 @@
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* @ModelId: Processor model ID
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* @ModelId: Processor model ID
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* @FamilyId: Processor family ID
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* @FamilyId: Processor family ID
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* @LapicBase: Local APIC MMIO base
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* @LapicBase: Local APIC MMIO base
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* @HasX2Apic: If set, x2APIC is supported
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*/
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*/
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typedef struct {
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typedef struct {
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UCHAR ModelId;
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UCHAR ModelId;
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USHORT FamilyId : 12;
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USHORT FamilyId : 12;
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VOID *LapicBase;
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VOID *LapicBase;
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UCHAR HasX2Apic : 1;
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} MCB;
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} MCB;
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#endif /* !_MACHINE_MCB_H_ */
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#endif /* !_MACHINE_MCB_H_ */
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