stos/amd64: lapic: Add IPI def groundwork

Signed-off-by: Chloe M. <chloe@mensia.org>

paw/stos/head/arch/amd64/lapic.h

@@ -12,6 +12,50 @@
 #include <stdef.h>
 #include <hal/kpcr.h>
 
+/*
+ * Destination shorthand values for inter-processor
+ * interrupts.
+ *
+ * @IPI_XND_NONE:  No shorthand
+ * @IPI_XND_SELF:  Self shorthand
+ * @IPI_XND_AIS:   All including self shorthand
+ * @IPI_XND_AES:   All exclduing self shorthand
+ */
+typedef enum {
+    IPI_XND_NONE,
+    IPI_XND_SELF,
+    IPI_XND_AIS,
+    IPI_XND_AES
+} IPI_SHORTHAND;
+
+/*
+ * Delivery mode values for inter-processor
+ * interrupts.
+ *
+ * @IPI_DELMOD_FIXED:       Deliver a specific interrupt vector to a slutty core~
+ * @IPI_LOWPRI:             Equivalent to a FIXED IPI but lowest priority
+ * @IPI_DELMOD_SMI:         Sends an SMI, we don't use this
+ * @IPI_DELMOD_RESERVED:    Reserved
+ * @IPI_DELMOD_NMI:         Deliver a non-maskable interrupt
+ * @IPI_DELMOD_INIT:        Deliver an INIT IPI to a processor
+ * @IPI_DELMOD_STARTUP:     Deliver a STARTUP IPI to a processor
+ */
+typedef enum {
+    IPI_DELMOD_FIXED,
+    IPI_DELMOD_LOWPRI,
+    IPI_DELMOD_SMI,
+    IPI_DELMOD_RESERVED,
+    IPI_DELMOD_NMI,
+    IPI_DEMOD_INIT,
+    IPI_DELMOD_STARTUP
+} IPI_DELMOD;
+
+/* IPI Delivery status bits */
+#define IPI_DELSTAT_PENDING BIT(0)
+
+/* IPI Destination mode */
+#define IPI_DELMOD_LOGICAL BIT(0)
+
 /*
  * Initialize the Local APIC unit for the current
  * processor.