stos/amd64: Impl phase 1 processor init

Signed-off-by: Chloe M. <chloe@mensia.org>
2026-06-22 19:15:58 +00:00
parent 2127bd8216
commit e3954277f8
4 changed files with 99 additions and 0 deletions
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description:  Kernel processor control region
+ * Author:       Chloe M.
+ */
+
+#include <hal/kpcr.h>
+#include <ex/trace.h>
+#include <machine/cpuid.h>
+#include <stdef.h>
+
+#define DTRACE(Fmt, ...) \
+    TRACE("[ CPU ]: " Fmt, ##__VA_ARGS__)
+
+static VOID
+ProcessorIdentify(MCB *Mcb)
+{
+    ULONG Eax, Unused;
+    UCHAR ModelLow, ModelHigh;
+    UCHAR FamilyLow, FamilyHigh;
+
+    if (Mcb == NULL) {
+        return;
+    }
+
+    CPUID(1, Eax, Unused, Unused, Unused);
+
+    /* Extarct the model ID */
+    ModelLow = (Eax >> 4) & 0xF;
+    ModelHigh = (Eax >> 16) & 0xF;
+    Mcb->ModelId = (ModelHigh << 4) | ModelLow;
+
+    /* Extract the family ID */
+    FamilyLow = (Eax >> 8) & 0xF;
+    FamilyHigh = (Eax >> 20) & 0xFF;
+    Mcb->FamilyId = (FamilyHigh << 4) | FamilyLow;
+
+    /* Informational logging */
+    DTRACE("model  : %X\n", Mcb->ModelId);
+    DTRACE("family : %X\n", Mcb->FamilyId);
+}
+
+VOID
+HalKpcrP1Init(KPCR *Kpcr)
+{
+    MCB *Mcb;
+
+    if (Kpcr == NULL) {
+        return;
+    }
+
+    Mcb = &Kpcr->Mcb;
+    ProcessorIdentify(Mcb);
+}