stos/amd64: Impl phase 1 processor init

Signed-off-by: Chloe M. <chloe@mensia.org>

paw/stos/head/arch/amd64/mcb.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description:  Machine core block
+ * Author:       Chloe M.
+ */
+
+#ifndef _MACHINE_MCB_H_
+#define _MACHINE_MCB_H_ 1
+
+#include <stdef.h>
+
+/*
+ * The machine-core block contains machine specific
+ * processor information
+ *
+ * @ModelId:    Processor model ID
+ * @FamilyId:   Processor family ID
+ */
+typedef struct {
+    UCHAR ModelId;
+    USHORT FamilyId : 12;
+} MCB;
+
+#endif  /* !_MACHINE_MCB_H_ */

paw/stos/head/hal/kpcr.h

@@ -10,15 +10,25 @@
 #define _HAL_KPCR_H_ 1
 
 #include <stdef.h>
+#include <machine/mcb.h>
 
 /*
  * The kernel processor control region contains MI
  * information about the processor.
  *
  * @CoreId:  Processor core ID assigned by us
+ * @Mcb:     Machine-core block
  */
 typedef struct {
     USHORT CoreId;
+    MCB Mcb;
 } KPCR;
 
+/*
+ * Phase 1 initialization of processor
+ *
+ * @Kpcr: KPCR to initialize
+ */
+VOID HalKpcrP1Init(KPCR *Kpcr);
+
 #endif  /* !_HAL_KPCR_H_ */