stos/amd64: Impl phase 1 processor init

Signed-off-by: Chloe M. <chloe@mensia.org>

paw/stos/arch/amd64/cpu/init.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description:  Kernel processor control region
+ * Author:       Chloe M.
+ */
+
+#include <hal/kpcr.h>
+#include <ex/trace.h>
+#include <machine/cpuid.h>
+#include <stdef.h>
+
+#define DTRACE(Fmt, ...) \
+    TRACE("[ CPU ]: " Fmt, ##__VA_ARGS__)
+
+static VOID
+ProcessorIdentify(MCB *Mcb)
+{
+    ULONG Eax, Unused;
+    UCHAR ModelLow, ModelHigh;
+    UCHAR FamilyLow, FamilyHigh;
+
+    if (Mcb == NULL) {
+        return;
+    }
+
+    CPUID(1, Eax, Unused, Unused, Unused);
+
+    /* Extarct the model ID */
+    ModelLow = (Eax >> 4) & 0xF;
+    ModelHigh = (Eax >> 16) & 0xF;
+    Mcb->ModelId = (ModelHigh << 4) | ModelLow;
+
+    /* Extract the family ID */
+    FamilyLow = (Eax >> 8) & 0xF;
+    FamilyHigh = (Eax >> 20) & 0xFF;
+    Mcb->FamilyId = (FamilyHigh << 4) | FamilyLow;
+
+    /* Informational logging */
+    DTRACE("model  : %X\n", Mcb->ModelId);
+    DTRACE("family : %X\n", Mcb->FamilyId);
+}
+
+VOID
+HalKpcrP1Init(KPCR *Kpcr)
+{
+    MCB *Mcb;
+
+    if (Kpcr == NULL) {
+        return;
+    }
+
+    Mcb = &Kpcr->Mcb;
+    ProcessorIdentify(Mcb);
+}

paw/stos/head/arch/amd64/mcb.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description:  Machine core block
+ * Author:       Chloe M.
+ */
+
+#ifndef _MACHINE_MCB_H_
+#define _MACHINE_MCB_H_ 1
+
+#include <stdef.h>
+
+/*
+ * The machine-core block contains machine specific
+ * processor information
+ *
+ * @ModelId:    Processor model ID
+ * @FamilyId:   Processor family ID
+ */
+typedef struct {
+    UCHAR ModelId;
+    USHORT FamilyId : 12;
+} MCB;
+
+#endif  /* !_MACHINE_MCB_H_ */

paw/stos/head/hal/kpcr.h

@@ -10,15 +10,25 @@
 #define _HAL_KPCR_H_ 1
 
 #include <stdef.h>
+#include <machine/mcb.h>
 
 /*
  * The kernel processor control region contains MI
  * information about the processor.
  *
  * @CoreId:  Processor core ID assigned by us
+ * @Mcb:     Machine-core block
  */
 typedef struct {
     USHORT CoreId;
+    MCB Mcb;
 } KPCR;
 
+/*
+ * Phase 1 initialization of processor
+ *
+ * @Kpcr: KPCR to initialize
+ */
+VOID HalKpcrP1Init(KPCR *Kpcr);
+
 #endif  /* !_HAL_KPCR_H_ */

paw/stos/init/init.c

@@ -10,6 +10,7 @@
 #include <ke/stos.h>
 #include <ke/bpal.h>
 #include <hal/serial.h>
+#include <hal/kpcr.h>
 #include <drivers/bootvid/fbio.h>
 #include <mm/pmm.h>
 #include <stdef.h>
@@ -17,6 +18,9 @@
 #define DTRACE(Fmt, ...) \
     TRACE("[ INIT ]: " Fmt, ##__VA_ARGS__)
 
+/* Globals */
+static KPCR BootstrapCore;
+
 /*
  * Display a boot banner
  */
@@ -47,4 +51,7 @@ KiKernelEntry(VOID)
 
     /* Initialize physical memory */
     MmInitPmm();
+
+    /* Phase 1 initialization the bootstrap core */
+    HalKpcrP1Init(&BootstrapCore);
 }