54faa60aca
stos/amd64: mp: Add multiprocessing groundwork
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-27 14:25:19 -05:00
1020db0f41
stos/amd64: lapic: Add helper to obtain Local APIC ID
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-27 14:24:05 -05:00
89e87fc525
stos/amd64: lapic: Clean up LAPIC IPI code
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-27 14:23:44 -05:00
e966cec4cd
stos/amd64: lapic: Calibrate the Local APIC timer
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-27 17:20:25 +00:00
1bebf4d37b
stos/amd64: lapic: Add support for IPIs
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-27 02:56:28 +00:00
e65af3fce0
stos/amd64: lapic: Fully enable Local APIC
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-26 20:56:57 +00:00
74d68ead72
stos/amd64: lapic: Detect if x2APIC mode is present
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-26 20:46:27 +00:00
fd30fc5e04
stos/amd64: cpu: Save Local APIC base in MCB
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-26 20:31:09 +00:00
38310e4f23
stos/amd64: cpu: Hardware enable Local APIC
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-26 20:22:20 +00:00
221cfc1893
stos/amd64: cpu: Add Local APIC driver stub
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-26 19:56:41 +00:00
9b1f4dde43
stos/amd64: cpu: Save KPCR in IA32_GS_BASE
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-24 05:49:59 +00:00
23746a2918
stos: ex: Add per-cpu pool allocator groundwork
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-24 05:05:39 +00:00
b8a80c1bd0
stos: knot: Fix up knot reasons for consistency
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 23:49:50 +00:00
531a027122
stos/amd64: cpu: Default to IRQL_PASSIVE on startup
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We cannot be certain that the CR8 register will be zeroed by the time we
have control passed to us, therefore it is wise to set it ourselves.
Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 22:05:02 +00:00
114cc434d2
stos/amd64: intr: Add IRQL management
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 22:01:52 +00:00
27c6ca8125
stos/amd64: cpu: Add HAL interrupt registration
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 21:20:09 +00:00
b6d4a1c963
stos/amd64: cpu: Add exception handling groundwork
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 19:11:14 +00:00
333331171d
stos/amd64: cpu: Obtain more processor info
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 07:03:35 +00:00
32a1463b92
stos: hal: Implement HalMmuForkVas()
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 23:27:04 +00:00
5b30974cb0
stos/amd64: mmu: Implement page mapping
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 22:35:42 +00:00
532e46c62f
stos: hal: Add virtual address space helpers
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 21:46:51 +00:00
e3954277f8
stos/amd64: Impl phase 1 processor init
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 19:15:58 +00:00
6f222ae96c
stos: init: Add kernel C entry
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 00:43:03 +00:00
d46ce89f83
stos/amd64: Load the GDT
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 00:23:12 +00:00
71de0c20b8
build: Implement build pipeline
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-21 23:29:51 +00:00
Chloe M.