23746a2918
stos: ex: Add per-cpu pool allocator groundwork
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-24 05:05:39 +00:00
531a027122
stos/amd64: cpu: Default to IRQL_PASSIVE on startup
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We cannot be certain that the CR8 register will be zeroed by the time we
have control passed to us, therefore it is wise to set it ourselves.
Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 22:05:02 +00:00
b6d4a1c963
stos/amd64: cpu: Add exception handling groundwork
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 19:11:14 +00:00
333331171d
stos/amd64: cpu: Obtain more processor info
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-23 07:03:35 +00:00
e3954277f8
stos/amd64: Impl phase 1 processor init
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Signed-off-by: Chloe M. <chloe@mensia.org >
2026-06-22 19:15:58 +00:00
Chloe M.