Chloe M.
68 lines
2.6 KiB
C
68 lines
2.6 KiB
C
/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Local APIC registers
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* Author: Chloe M.
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*/
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#ifndef _MACHINE_LAPICREG_H_
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#define _MACHINE_LAPICREG_H_ 1
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#include <stdef.h>
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/* LAPIC register offsets */
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#define LAPIC_ID 0x0020U /* ID Register */
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#define LAPIC_VERSION 0x0030U /* Version Register */
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#define LAPIC_TPR 0x0080U /* Task Priority Register */
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#define LAPIC_APR 0x0090U /* Arbitration Priority Register */
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#define LAPIC_PPR 0x00A0U /* Processor Priority Register */
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#define LAPIC_EOI 0x00B0U /* End Of Interrupt Register */
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#define LAPIC_RRD 0x00C0U /* Remote Read Register */
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#define LAPIC_LDR 0x00D0U /* Logical Destination Register */
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#define LAPIC_DFR 0x00E0U /* Destination Format Register */
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#define LAPIC_SVR 0x00F0U /* Spurious Vector Register */
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#define LAPIC_ISR 0x0100U /* In service register (max=0x0220) */
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#define LAPIC_TMR 0x0180U /* Trigger Mode Register (max=0x0220) */
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#define LAPIC_IRR 0x0200U /* Interrupt Request Register (max=0x0270) */
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#define LAPIC_ERR 0x0280U /* Error Status Register */
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#define LAPIC_ICRLO 0x0300U /* Interrupt Command Low Register */
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#define LAPIC_ICRHI 0x0310U /* Interrupt Command High Register */
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#define LAPIC_LVT_TMR 0x0320U /* LVT Timer Register */
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#define LAPIC_DCR 0x03E0U /* Divide Configuration Register (for timer) */
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#define LAPIC_INIT_CNT 0x0380U /* Initial Count Register (for timer) */
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#define LAPIC_CUR_CNT 0x0390U /* Current Count Register (for timer) */
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/*
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* The x2APIC register space is accessed via
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* RDMSR/WRMSR instructions. The below defines
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* the base MSR address for the register space.
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*/
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#define x2APIC_MSR_BASE 0x00000800
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/*
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* To hardware enable, OR the value of the IA32_APIC_BASE
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* MSR with LAPIC_HW_ENABLE and rewrite it.
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*
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* To software enable, OR the value of the SVR with
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* LAPIC_SW_ENABLE and rewrite it.
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*
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* LAPIC_SW_ENABLE has the low 8 bits set as some hardware
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* requires the spurious vector to be hardwired to 1s so
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* we'll go with that to be safe.
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*/
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#define LAPIC_HW_ENABLE BIT(11)
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#define LAPIC_SW_ENABLE (BIT(8) | 0xFF)
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#define x2APIC_ENABLE_SHIFT 10
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/* LVT bits */
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#define LAPIC_LVT_MASK BIT(16)
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#define LVT_TMR_ONESHOT 0x00
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#define LVT_TMR_PERIODIC 0x01
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#define LVT_TMR_TSC_DEADLINE 0x02
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/* MSR for x2APICs only */
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#define LAPIC_SELF_IPI 0x083F
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#endif /* !_MACHINE_LAPICREG_H_ */
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