Chloe M.
171 lines
3.7 KiB
C
171 lines
3.7 KiB
C
/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Local APIC driver
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* Author: Chloe M.
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*/
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#include <machine/lapic.h>
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#include <machine/lapicreg.h>
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#include <machine/msr.h>
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#include <machine/cpuid.h>
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#include <hal/mmio.h>
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#include <drivers/acpi/tables.h>
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#include <drivers/acpi/acpi.h>
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#include <mm/vmm.h>
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#include <ex/trace.h>
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#include <ke/knot.h>
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#include <stdef.h>
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/*
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* Trace only on the bootstrap processor but not on any others
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* to avoid log spam...
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*/
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#define DTRACE_BSP(Fmt, ...) do { \
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ULONG ApicBase; \
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\
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ApicBase = MdRdmsr(IA32_APIC_BASE_MSR); \
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if (ISSET(ApicBase, BIT(8))) { \
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TRACE("[ LAPIC ]: " Fmt, ##__VA_ARGS__); \
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} \
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} while (0);
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/*
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* Returns true if the Local APIC unit is supported on the
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* current processor.
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*/
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static BOOLEAN
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LapicIsSupported(VOID)
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{
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ULONG Edx, Unused;
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CPUID(1, Unused, Unused, Unused, Edx);
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return ISSET(Edx, BIT(9)) != 0;
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}
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/*
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* Returns true if the CPU can operate its Local APIC unit
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* in the newer x2APIC mode.
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*/
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static BOOLEAN
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LapicHasX2Apic(VOID)
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{
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ULONG Ecx, Unused;
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CPUID(1, Unused, Unused, Ecx, Unused);
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return ISSET(Ecx, BIT(21)) != 0;
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}
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/*
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* Read a Local APIC register
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*
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* @Mcb: Machine core block
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* @Register: Register to read
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*/
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static UQUAD
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LapicRegRead(MCB *Mcb, ULONG Register)
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{
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ULONG *Base;
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UQUAD Value;
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if (!Mcb->HasX2Apic) {
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Base = PTR_OFFSET(Mcb->LapicBase, Register);
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Value = MMIORead32(Base);
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} else {
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Register >>= 4;
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Value = MdRdmsr(x2APIC_MSR_BASE + Register);
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}
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return Value;
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}
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/*
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* Write a value to a Local APIC register space
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*
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* @Mcb: Machine core block
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* @Register: Register to read
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* @Value: Value to write
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*/
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static VOID
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LapicRegWrite(MCB *Mcb, ULONG Register, UQUAD Value)
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{
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ULONG *Base;
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if (!Mcb->HasX2Apic) {
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Base = PTR_OFFSET(Mcb->LapicBase, Register);
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MMIOWrite32(Base, (ULONG)Value);
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} else {
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Register >>= 4;
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MdWrmsr(x2APIC_MSR_BASE + Register, Value);
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}
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}
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/*
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* Enable the Local APIC unit
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*
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* @Mcb: Machine core block
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*/
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static VOID
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LapicEnable(MCB *Mcb)
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{
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UQUAD ApicBase;
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ULONG Svr, Version;
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const CHAR *mode;
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const CHAR *type = "discrete 82489DX";
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/* Hardware enable the Local APIC unit */
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ApicBase = MdRdmsr(IA32_APIC_BASE_MSR);
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ApicBase |= LAPIC_HW_ENABLE;
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ApicBase |= Mcb->HasX2Apic << x2APIC_ENABLE_SHIFT;
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MdWrmsr(IA32_APIC_BASE_MSR, ApicBase);
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/* Software enable the Local APIC unit */
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Svr = LapicRegRead(Mcb, LAPIC_SVR);
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Svr |= LAPIC_SW_ENABLE;
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LapicRegWrite(Mcb, LAPIC_SVR, Svr);
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/* Check the type */
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Version = LapicRegRead(Mcb, LAPIC_VERSION);
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if ((Version & 0xFF) > 0) {
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type = "integrated";
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}
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mode = Mcb->HasX2Apic ? "x2apic" : "xapic";
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DTRACE_BSP("enabled %s %s\n", type, mode);
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}
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VOID
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MdLapicInit(KPCR *Kpcr)
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{
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ACPI_MADT *Madt;
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MCB *Mcb;
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if (Kpcr == NULL) {
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KeKnot(
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KNOT_MISC,
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"lapic: failed to initialize lapic driver\n"
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);
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}
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if (!LapicIsSupported()) {
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KeKnot(
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KNOT_MISSING_HARDWARE,
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"lapic: local apic not supported\n"
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);
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}
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/* Obtain the ACPI MADT table */
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Madt = AcpiQuery("APIC");
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if (Madt == NULL) {
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KeKnot(KNOT_MISC, "lapic: could not obtain MADT\n");
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}
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Mcb = &Kpcr->Mcb;
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Mcb->LapicBase = PMA_TO_VMA((UPTR)Madt->LapicAddr);
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Mcb->HasX2Apic = LapicHasX2Apic();
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/* Enable the Local APIC */
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LapicEnable(Mcb);
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}
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